2-mbit (256k x 8) mobl ? static ram cy62138ev30 mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05577 rev. *a revised february 14, 2006 features ? very high speed: 45 ns ? wide voltage range: 2.20v ? 3.60v ? pin-compatible with cy62138cv30 ? ultra-low standby power ? typical standby current: 1 a ? maximum standby current: 7 a ? ultra-low active power ? typical active current: 2 ma @ f = 1 mhz ? easy memory expansion with ce and oe features ? automatic power-down when deselected ? cmos for optimum speed/power ? offered in pb-free 36-ball bga package functional description [1] the cy62138ev30 is a high-performance cmos static ram organized as 256k words by 8 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-dow n feature that significantly reduces power consumption. the device can be put into standby mode reducing power consumption when deselected (ce high). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low and we low). note: 1. for best practice recommendations, please refer to the cypres s application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram a 1 column decoder row decoder sense amps data in drivers power down we oe i/o 0 i/o 1 i/o 2 i/o 3 256k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 12 ce a 13 a 14 a 15 a 16 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 17 [+] feedback [+] feedback
cy62138ev30 mobl ? document #: 38-05577 rev. *a page 2 of 9 pin configuration [2] product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min. typ. [3] max. typ. [3] max. typ. [3] max. typ. [3] max. cy62138ev30ll 2.2 3.0 3.6 45 2 2.5 15 20 1 7 notes: 2. nc pins are not connected on the die. 3. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. a 15 v cc a 13 a 12 a 5 nc we a 7 i/o 4 i/o 5 a 4 i/o 6 i/o 7 v ss a 11 a 10 a 1 v ss i/o 0 a 2 a 8 a 6 a 3 a 0 v cc i/o 1 i/o 2 i/o 3 a 17 nc a 16 ce oe a 9 a 14 d e b a c f g h nc top view fbga [+] feedback [+] feedback
cy62138ev30 mobl ? document #: 38-05577 rev. *a page 3 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. ............ .......... 55c to +125c supply voltage to ground potential ........................................ ?0.3v to v cc(max) + 0.3v dc voltage applied to outputs in high-z state [4,5] ......................... ?0.3v to v cc(max) + 0.3v dc input voltage [4,5] ......................?0.3v to v cc(max) + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma product range ambient temperature v cc [6] cy62138ev30ll industrial ?40c to +85c 2.2v to 3.6v electrical characteristics over the operating range parameter description test conditions cy62138ev30-45 unit min. typ. [3] max. v oh output high voltage i oh = ?0.1 ma v cc = 2.20v 2.0 v i oh = ?1.0 ma v cc = 2.70v 2.4 v v ol output low voltage i ol = 0.1 ma v cc = 2.20v 0.4 v i ol = 2.1 ma v cc = 2.70v 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3v v v cc = 2.7v to 3.6v 2.2 v cc + 0.3v v v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels 15 20 ma f = 1 mhz 2 2.5 ma i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v, v in < 0.2v), f = f max (address and data only), f = 0 (oe , and we ), v cc = 3.60v 17 a i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v 17 a capacitance for all packages [7] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ.) 10 pf c out output capacitance 10 pf notes: 4. v il(min.) = ?2.0v for pulse durations less than 20 ns. 5. v ih(max) = v cc +0.75v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 s ramp time from 0 to v cc (min.) and 200 s wait time after v cc stabilization. [+] feedback [+] feedback
cy62138ev30 mobl ? document #: 38-05577 rev. *a page 4 of 9 thermal resistance parameter description test conditions bga unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 72 c/w jc thermal resistance (junction to case) 8.86 c/w ac test loads and waveforms parameters 2.50v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min. typ. [3] max. unit v dr v cc for data retention 1 v i ccdr data retention current v cc = 1v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 0.8 3 a t cdr [7] chip deselect to data retention time 0 ns t r [8] operation recovery time t rc ns v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: thvenin equivalent all input pulses r th r1 fall time: 1 v/ns rise time: 1 v/ns data retention waveform notes: 7. tested initially and after any design or proc ess changes that may affect these parameters. 8. full device ac operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s. 1.5v t cdr v dr > 1.5 v data retention mode t r ce v cc v cc (min.) [+] feedback [+] feedback
cy62138ev30 mobl ? document #: 38-05577 rev. *a page 5 of 9 switching characteristics (over the operating range) [9] parameter description 45 ns unit min. max. read cycle t rc read cycle time 45 ns t aa address to data valid 45 ns t oha data hold from address change 10 ns t ace ce low to data valid 45 ns t doe oe low to data valid 22 ns t lzoe oe low to low z [10] 5ns t hzoe oe high to high z [10,11] 18 ns t lzce ce low to low z [10] 10 ns t hzce ce high to high z [10, 11] 18 ns t pu ce low to power-up 0 ns t pd ce high to power-up 45 ns write cycle [12] t wc write cycle time 45 ns t sce ce low to write end 35 ns t aw address set-up to write end 35 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 35 ns t sd data set-up to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high z [10, 11] 18 ns t lzwe we high to low z [10] 10 ns switching waveforms read cycle no. 1 (address transition controlled) [13, 14] notes: 9. test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 v/ns), timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 10. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 11. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high-impedance state. 12. the internal write time of the me mory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hol d timing should be referenced to the edge of the signal that terminates the write. 13. device is continuously selected. oe , ce = v il . 14. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha [+] feedback [+] feedback
cy62138ev30 mobl ? document #: 38-05577 rev. *a page 6 of 9 read cycle no. 2 (oe controlled) [14, 15] write cycle no. 1 (we controlled) [16, 18] notes: 15. address valid prior to or coincident with ce transition low. 16. data i/o is high impedance if oe = v ih . 17. during this period, the i/os are in output state and input signals should not be applied. 18. if ce goes high simultaneously with we high, the output remains in high-impedance state. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current address t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note 17 t sce [+] feedback [+] feedback
cy62138ev30 mobl ? document #: 38-05577 rev. *a page 7 of 9 write cycle no. 2 (ce controlled) [16, 18] write cycle no. 3 (we controlled, oe low) [18] switching waveforms (continued) t wc data in valid t aw t sa t pwe t ha t hd t sd t sce ce address we data i/o oe data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce t hzwe data in valid note 17 t pwe t sce we truth table ce we oe inputs/outputs mode power h x x high z deselect/power-down standby (i sb ) l h l data out (i/o 0 ?i/o 7 ) read active (i cc ) l h h high z output disabled active (i cc ) l l x data in (i/o 0 ?i/o 7 ) write active (i cc ) [+] feedback [+] feedback
cy62138ev30 mobl ? document #: 38-05577 rev. *a page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark, and more battery life is a trademark, of cypress semicond uctor. all product and company names mentioned in this document may be t he trademarks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 45 CY62138EV30LL-45BVXI 51-85149 36-ball very fine pitch bga (6 mm 8 mm 1 mm) (pb-free) industrial package diagrams a 1 a1 corner 0.75 0.75 ?0.300.05(36x) ?0.25mcab ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 36-ball vfbga (6 x 8 x 1 mm) (51-85149) 51-85149-*c [+] feedback [+] feedback
cy62138ev30 mobl ? document #: 38-05577 rev. *a page 9 of 9 document history page document title: cy62138ev30 2-mbit (256k x 8) mobl ? static ram document number: 38-05577 rev. ecn no. issue date orig. of change description of change ** 237432 see ecn aju new data sheet *a 427817 see ecn nxr removed 35 ns speed bin removed ?l? version removed 32-pin tsopii package from product offering. changed ball c3 from dnu to nc. removed the redundant footnote on dnu. moved product portfolio from page # 3 to page #2. changed i cc (max) value from 2 ma to 2.5 ma and i cc (typ) value from 1.5 ma to 2 ma at f = 1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max =1/t rc changed i sb1 and i sb2 typ. values from 0.7 a to 1 a and max. values from 2.5 a to 7 a. changed v cc stabilization time in footnote #7 from 100 s to 200 s changed the ac test load capacitance from 50pf to 30pf on page# 4 changed v dr from 1.5v to 1v on page# 4. changed i ccdr from 1 a to 3 a in the data retention characteristics table on page # 4. corected t r in data retention characteristics from 100 s to t rc ns changed t oha , t lzce , t lzwe from 6 ns to 10 ns changed t hzoe , t hzce , t hzwe from 15 ns to 18 ns changed t lzoe from 3 ns to 5 ns changed t sce and t aw from 40 ns to 35 ns changed t sd from 20 ns to 25 ns changed t pwe from 25 ns to 35 ns updated the ordering information table and replaced package name column with package diagram. [+] feedback [+] feedback
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